1. Field of the Invention
This invention relates to a shared bus interface system for electronic systems which minimizes the number of pins required for high-integration processor chips.
2. Description of the Related Art
Most electronic systems and main memory systems, such as multimedia and computer systems, include microprocessor chips that use a system bus to interface to peripheral devices and a memory bus to interface to main memory. As a result of recent advances in semiconductor manufacturing technologies, the speed of operation and the level of integration of microprocessor chips have increased significantly. Microprocessor chips with integrated memory controllers, cache controllers and system interface controllers are now available. These high-integration chips have mostly been used for mid-range or low-end applications where power consumption, motherboard area or system cost were the primary concerns. However, ever increasing clock frequencies on current microprocessors has resulted in memory access time becoming the critical performance limiter. To deal with memory latency, even high-end versions of microprocessors are being implemented with a memory controller on the processor chip.
While an integrated memory controller definitely improves the memory access time by eliminating the cycles which are necessary to go through a system bus, it also uses a large number of pins for communicating to memory chips. High-end processors can use hundreds of pins exclusively to communicate with main memory chips. In cases where a second-level or third-level cache interface and a peripheral interface used for I/O also needs to be supported, the total number of required processor pins may become excessive for a realistic or economical implementation. Even for mid-range or low-end chips, where there is no need for a cache interface, the total number of pins required for memory, system I/O and any other feature specific interface may become too many for a low cost package. The die size also may become limited by the number of pin drivers required, where the chip may need to be manufactured using a die size which is greater than otherwise needed to contain the logic.
There have been several high-integration products integrating a processor, memory controller and a system bus interface on a single chip, such as, for example, Intel's 386SL and 486SL processors and Sun Microsystems' MicroSPARC.TM. I and II processors. However, all of these integrated circuit chips implement separate memory busses and system bus interfaces. Future generation processors will require 128-512 bit memory interface with 14-40 extra bits for address/control lines and 16-64 bits for error correction, which creates substantially more pressure on pin-count and die-size. One solution in addressing the pin-count issue, is the use of a very high speed memory interface, however, there is a technology risk involved in this solution because high-end processors are usually manufactured with new semiconductor processes.
Therefore, there is a need for a simple and economical solution that minimizes the number of pins required for a high-end integration processor chip without compromising the performance. It is expected that synchronous-dynamic random access memories (S-DRAM) will be increasingly used in the electronic systems market, and, therefore, a solution compatible with S-DRAM technology is economically viable.
To understand the concept of the present invention, it is helpful to review S-DRAM technology. Dynamic random access memory (DRAM) components provide an inexpensive solid state storage technology for digital systems. The digital information is maintained in the form of a charge stored on a two dimensional array of capacitors. There are two types of DRAMs: synchronous and asynchronous. In a S-DRAM, the time base is shared between the controller/processor and the DRAM component and is independent of the control signals sent to the S-DRAM. In an asynchronous DRAM, the control signals communicate the timing information in an asynchronous manner. Synchronous interfaces are desirable because information can be transferred at a higher rate.